1. Field of the Invention
This invention relates to logic circuits, and more particularly, to decoder circuits.
2. Description of the Related Art
Memory arrays are accessed at specific locations by providing an address. Each address has a certain number of bits. Larger memory arrays with a greater number of locations require a greater number of address bits. Thus, larger memory arrays having a larger address space require more logic to decode the address. As the demands for memory space increase as technology advances, the address space and thus the amount of required address decoder logic also increases. Often times with larger address decoders, the large amount of logic presents a bottleneck to memory access speed. Furthermore, the additional logic required for a larger address space can consume a significant amount of circuit area, power, and other resources. With the demand for increasing speed and greater computing resources (including larger memory) competing for circuit area and power, the problems associated with the increasing demands of circuit area, power, and speed created by the demand for decoding large address spaces are exacerbated.